ADT7476A
http://onsemi.com
12
connected to a common SMBALERT
line connected to the
master. If a devices SMBALERT
line goes low, the
following procedure occurs:
1. SMBALERT
is pulled low.
2. The master initiates a read operation and sends the
alert response address (ARA = 0001 100). This is
a general call address that must not be used as a
specific device address.
3. The device whose SMBALERT
output is low
responds to the alert response address, and the
master reads its device address. The address of this
device is now known and can be interrogated per
usual.
4. If more than one devices SMBALERT
output is
low, the one with the lowest device address has
priority in accordance with normal SMBus
arbitration.
5. Once the ADT7476A responds to the alert
response address, the master must read the status
registers, and SMBALERT
is cleared only if the
error condition goes away.
SMBus Timeout
The ADT7476A includes an SMBus timeout feature. If
there is no SMBus activity for 35 ms, the ADT7476A
assumes the bus is locked and releases the bus. This prevents
the device from locking or holding the SMBus expecting
data. Some SMBus controllers cannot handle the SMBus
timeout feature, so if necessary, it can be disabled.
Table 6. CONFIGURATION REGISTER 1 (REG. 0x40)
Bit
Description
[6] TODIS
0: SMBus Timeout Enabled (Default)
1: SMBus Timeout Disabled
Virus Protection
To prevent rogue programs or viruses from accessing
critical ADT7476A register settings, the lock bit can be set.
Setting Bit 1 of Configuration Register 1 (0x40) sets the
lock bit and locks critical registers. In this mode, certain
registers can no longer be written to until the ADT7476A is
powered down and powered up again. For more information
on which registers are locked see Table 49.
Voltage Measurement Input
The ADT7476A has four external voltage measurement
channels. It can also measure its own supply voltage, V
CC
.
Pin 20 to Pin 23 can measure 5.0 V, 12 V, and 2.5 V
supplies, and the processor core voltage V
CCP
(0 V to 3 V
input). The V
CC
supply voltage measurement is carried out
through the V
CC
pin (Pin 4). The 2.5 V input can be used to
monitor a chipset supply voltage in computer systems.
Analog-to-Digital Converter
All analog inputs are multiplexed into the on-chip,
successive-approximation, analog-to-digital converter,
which has a resolution of 10 bits. The basic input range is 0 V
to 2.25 V, but the inputs have built-in attenuators to allow
measurement of 2.5 V, 3.3 V, 5.0 V, 12 V, and the processor
core voltage V
CCP
without any external components. To
allow the tolerance of these supply voltages, the ADC
produces an output of 3/4 full scale (768 dec or 300 hex) for
the nominal input voltage, giving it adequate headroom to
cope with overvoltages.
Input Circuitry
The internal structure for the analog inputs is shown in
Figure 24 The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first-order
low-pass filter that gives input immunity to high frequency
noise.
Figure 24. Structure of Analog Inputs
17.5 kW
52.5 kW
V
CCP
35 pF
45 kW
94 kW
+2.5V
IN
30 pF
68 kW
71 kW
V
CC
30 pF
93 kW
47 kW
+5V
IN
30 pF
183.6 kW
30 kW
+12V
IN
30 pF
MUX
Table 7. VOLTAGE MEASUREMENT REGISTERS
Register
Description
Default
0x20
2.5 V Reading
0x00
0x21
V
CCP
Reading
0x00
0x22
V
CC
Reading
0x00
0x23
5.0 V Reading
0x00
0x24
12 V Reading
0x00
Voltage Limit Registers
Associated with each voltage measurement channel is a
high and low limit register. Exceeding the programmed high
or low limit causes the appropriate status bit to be set.
Exceeding either limit can also generate SMBALERT
interrupts.
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